FIG. 10 is a block diagram of a conventional frequency error estimating circuit that is shown in, for example, “Performance of a Simple Delay-Multiply-Average Technique for Frequency Estimation”, S. N. Crozier, et al., Canadian Conference on Electrical and Computer Engineering, paper WM10.3, Sep. 13–16, 1992. In FIG. 10, 1 denotes a received signal, 2 denotes a sampling section that samples the received signal 1 at a symbol rate, 101 denotes a multiplier that multiplies a sampled received signal 3 and removes a modulation component from the signal, 102 denotes a delay detector that sequentially detects delay of an output of the multiplier 101, 103 denotes an averaging filter that averages an output of the delay detector 102 and suppresses a noise component, 104 denotes a coordinate converter that calculates a phase component of a received signal based on an output of the averaging filter 103, and 105 denotes a divider that calculates a frequency error from the phase component of the received signal.
The operation of the conventional frequency error estimating circuit will be explained below. The received signal 1 has been modulated according to an M-phase PSK (Phase Shift Keying) modulation system, and is prescribed by the following expression 1.r(t)=A(t)exp[j{θ(t)+Δωt}]  (1)where r(t) represents the received signal 1, A(t) represents an amplitude component, and θ(t) represents a modulation phase component. The phase component of the received signal includes a frequency error Δωt. In order to simplify the explanation, it is assumed that the received signal 1 does not contain a noise component.
The sampling section 2 sequentially samples the received signal 1 at a symbol rate. The received signal 3 after being sampled is expressed by the following expression 2.r(nT)=A(nT)exp[{θ(nT)+ΔωnT}]  (2)where r(nT) represents the sampled received signal 3, T represents a symbol period, and n represents a natural number. A modulation phase component θ(nT) becomes as follows according to the M-phase PSK modulation system.θ(nT)=2πk/M  (3)                k=0, 1, . . . , M−1)The modulation phase component θ(nT) takes M values in total at equal intervals within a range of 0 to 2π.        
The multiplier 101 multiplies the received signal 3 by a predetermined modulation multiple-value M to remove the modulation phase component from the received signal 3. A signal r1(nT) after the multiplication is expressed by the following expression 4.r1(nT)=A(nT)exp[jM{θ(nT)+ΔωnT}]  (4)
It is clear that a modulation phase component Mθ(nT) after the M multiplication is an integral multiple of 2π from the above expression 3, and it is possible to disregard this component. In other words, the signal r1(nT) after the multiplication is expressed by the following expression 5.r1(nT)=A(nT)exp(jMΔωnT)  (5)
The delay detector 102 detects delay of the M-multiplied signal r1(nT) for a predetermined symbol period. When a symbol period in the processing of delay detection is D, a demodulated signal d1(nT) after the delay detection becomes as follows.
                                          d            1                    ⁡                      (            nT            )                          =                                            r              1                        ⁡                          (              nT              )                                ⁢                      r            1                    *                      (                          nT              -              DT                        )                                                  =                              A            ⁡                          (              nT              )                                ⁢                      A            ⁡                          (                              nT                -                DT                            )                                ⁢                      exp            (                          jMD              ⁢                                                          ⁢              Δω              ⁢                                                          ⁢              T                        ⁢                                                  )                              
where r1*(nT−DT) represents a conjugate complex of r1(nT−DT).
Assume that a Nyquist point has been selected as a sampling timing in the sampling section 2. As an amplitude component A(nT) of the received signal is always constant, the demodulated signal d1(nT) is expressed by the following expression 6.d1(nT)=exp(jMDΔωT)  (6)
The averaging filter 103 averages the demodulated signal d1(nT), after the delay detection, over a predetermined period of time, thereby to suppress a noise component contained in the received signal. As it is assumed here that a noise component is not contained in the received signal, the demodulated signal d1(nT) is output from the averaging filter 103 as it is.
The coordinate converter 104 converts the coordinates of the demodulated signal d1(nT) that are expressed in an orthogonal coordinate system on the phase plane into coordinates expressed in polar coordinates, and calculates a phase component MDΔωT of the demodulated signal d1(nT). Last, the divider 105 divides the phase component MDΔωT of the demodulated signal by MD, and outputs the frequency error ΔωT of the received signal over one symbol period T. An estimate range Δf (=Δω/2π) of the frequency error is expressed by the following expression 7.|Δf|<fs/2MD  (7)
where fs represents a symbol rate of the received signal.
Therefore, for example, when the number of symbol periods of the delay detection processing is D=1 in the QPSK modulation system (multiple number to be modulated M=4), it is possible to estimate frequency error up to ⅛ of the symbol rate fs. The frequency error thus estimated is used to control a local oscillator of a receiver like a VCO (Voltage Controlled Oscillator).
According to the conventional frequency error estimating circuit, it is necessary to make the symbol period D of the delay detector 103 as small as possible, in order to widen the estimate range Δf of the frequency error. However, when a local oscillator with low setting precision of frequency is used in the mobile communications of a low symbol rate, or when the received signal undergoes large Doppler shift like in the mobile satellite communications, the frequency error of the local oscillator with respect to the received signal might become larger than the estimate range Δf of the frequency error estimating circuit prescribed by the expression 7. Consequently, there has been a problem that it is not possible to accurately estimate the frequency error.
On the other hand, in order to estimate a large frequency error in the conventional frequency error estimating circuit, there has been a method of expanding the estimate range Δf of the frequency error by M times without performance of the multiplication processing of a received signal by the multiplier 101. According to this method, it is necessary to transmit known patterns for estimate of a frequency error separately from the normal data, in order to estimate the frequency error. Therefore, there has been a problem that the data transmission efficiency is lowered substantially.
Further, it is not possible to estimate a frequency error during reception of the normal data. Therefore, there has been a problem that it is not possible to accurately correct the frequency error and the communication quality is degraded when there is a large variation in the frequency error due to a move of the receiver during communications.
Therefore, the present invention has an object of providing a receiver and a frequency error estimating method capable of accurately estimating a frequency error without lowering the data transmission efficiency, even when a large frequency error occurs between a received signal and a local oscillator of the receiver.